Thin-Film Electronics by Spatial ALD: Achieving High Performance with Low Process Complexity

Abstract: Patterning thin-film transistors for 'printed electronics' applications can be challenging both for resolution and for alignment accuracy. This is particularly true for high-performance devices with submicron channel lengths, and for diverse and deformable substrates. Printing organic-based devices requires additional consideration of issues such as printing dynamics and orthogonality of solvents.  In this talk, I will describe alternative approaches to scalable thin-film electronics based on spatial atomic layer deposition (SALD) of metal oxides. Using the relatively high deposition speed of SALD, the conformality of the deposited layers, and the surface-sensitivity of the technique, we have explored both print-compatible high-performance vertical transistors, and patterned-by-printing circuitry. A reliable ZnO mobility above 10 cm2/Vs, on-off ratio above 107, and uniform threshold voltage values across the substrate give these approaches promise for large-area applications.

All seminars are held on Wednesdays from 12:00 noon-1:00 p.m. in the Bowen Hall Auditorium Room 222. A light lunch is provided at 11:30 a.m. in the Bowen Hall Atrium immediately prior to the seminar.